1. Field of the Invention
The present invention relates generally to a semiconductor package technology and, more particularly, to a wiring substrate capable of improving board level reliability (BLR), a semiconductor package having the wiring substrate, and a stack package using the semiconductor package.
2. Description of the Related Art
As small, thin and light semiconductor packages are pursued in the miniaturization of electronic mobile devices, capacities of semiconductor chips to be mounted on the semiconductor packages have increased. To increase the capacity of a semiconductor chip, a technology that can install more cells in a limited space of the semiconductor chip is required. Such a technology requires a patterning technology in precise micro-line widths and long development time. Alternatively, methods of high integration using semiconductor chips or semiconductor packages already developed, for example stacked chip packages with three-dimensionally stacked semiconductor chips and stack packages with three-dimensionally stacked semiconductor packages, have been actively studied recently. In other words, higher capacity has been reached by combining existing, e.g., already developed, multiple semiconductor chips or packages.
Three-dimensionally stacked chip packages, e.g., fabricated by three-dimensionally stacking a plurality of semiconductor chips, can accomplish high integration and effectively respond to requirements for light, thin and small semiconductor products. If reliability for the stacked semiconductor chips is not acquired, however, a yield decrease can occur. That is, if any one failed, e.g., bad, semiconductor chip is included in the stacked semiconductor chips, the final three-dimensionally stacked chip package as a whole fails without possibility of repair.
On the other hand, although three-dimensional stack packages fabricated by three-dimensionally stacking a plurality of semiconductor packages have a problem of too great a thickness compared with the stacked chip packages, high integration may be accomplished, and the problem of yield decrease of the three-dimensionally stacked stack packages may be overcome by using semiconductor packages that have passed a reliability test.
A stack package may be fabricated by stacking ball grid array (BGA) type semiconductor packages. A lower package of the stack package has a structure in which a semiconductor chip is mounted on the central part of the upper surface of a wiring substrate, sealed by a resin encapsulating section, and solder balls are formed on lower ball pads of the lower surface of the wiring substrate. Upper ball pads are uniformly formed on the upper surface of the wiring substrate outside the resin encapsulating section so that an upper package can be stacked on the lower package, e.g., by solder bonding. That is, solder balls of the upper package are attached on the upper ball pads of the lower package by way of solder bonding.
The solder balls of the lower-most package are used as external connection terminals of the overall stack package. That is, the stack package is connected to a motherboard through the solder balls of the lower package.
Because the lower package has the resin encapsulating section on the central part of the wiring substrate, an upwardly convex warp or deformation occurs in the central part of the wiring substrate. Because the lower ball pads formed on the wiring substrate of the lower package all have the same surface area, the solder balls have also all the same size.
Due to such upwardly convex warp or deformation in the wiring substrate of the lower package, the distances between the upper surface of a motherboard and lower ball pads at the central part of the lower package differ from the distances between the upper surface of the motherboard and lower ball pads on the periphery of the lower package (hereinafter referred to as ‘distance difference’). This distance difference decreases a solder bonding ability of the lower package to the motherboard.
To solve such a problem, and as disclosed in U.S. Patent Publication No. 2004/0222510, the surface areas of the lower ball pads gradually increase from the central part of the wiring substrate to the periphery thereof as the pad separation decreases in consideration of the warped shape of the lower package wiring substrate. Similarly, the surface areas of the lower ball pads gradually decrease from the central part of the wiring substrate to the periphery thereof as the pad separation increases.
With the above method, the problem due to the distance difference of the lower ball pads of the lower package may be decreased and thereby bonding reliability to the motherboard may be improved.
However, cracks may occur at junctions of solder balls located at the corners of the stack package when a board level reliability test for a stack package mounted on the motherboard is performed. The board level reliability test includes tests of drop impact, bending fatigue, temperature cycle and keypad strike. Particularly, cracks of the solder balls often occur during drop impact and temperature cycle testing.
Although the outermost solder balls have greater contact areas with lower ball pads than central solder balls, because mechanical stresses are substantially concentrated on the corners of the wiring substrate, e.g., during the board level reliability test, cracks undesirably occur at junctions of the outermost solder balls, especially those disposed at the corners of the wiring substrate.